The goal of this project is to design and implement programmable hardware monitors for securing processors. We are developing a complete framework including the hardware monitor architecture and its interface with a RISC-V processor as well as an operating system. A user can program our hardware monitors based on his/her requirements to employ them in different applications such a detecting security attacks, online profiling, and fuzzing.
The goal of this project is to design and open-source a Linux-capable, cache-coherent, RV64GC multicore processor. This processor is currently being developed by the University of Washington and Boston University, but it strives to be community-driven and infrastructure agnostic core, which is Pareto optimal in terms of power, performance, area and complexity. BlackParrot is ideal as the basis for a lightweight accelerator host, a standalone Linux core or as a hardware research platform.
The high-level goal of this project is to develop a silicon-photonic interconnect system that can improve performance of manycore processors and GPUs. This project has multiple sub-projects – 1) The first sub-project focuses on developing run-time system-level power management techniques for managing laser power and thermal-tuning power of silicon-photonic networks; 2) The second sub-project focuses on designing a unified on-chip/off-chip silicon-photonic network for next generation CPU-GPU systems; and 3) The third sub-project focuses on the design of novel cross-layer design automation methods for 2.5D-integrated heterogeneous systems with silicon-photonic networks, and the demonstration of the benefits of these 2.5D systems with respect to energy efficiency, robustness, and performance.
The objective of this project is to develop and demonstrate optical nanoantennas as an optical watermarking technology, which can be used to rapidly detect any insertion of malicious hardware Trojans in CMOS IC chips. We propose to strategically embed predefined structures in one or more layers of the metal stack within each standard cell while developing the standard cell library. These metal nanostructures can be engineered to produce unique optical signatures that are a function of their design and surrounding environment. Any modifications in the form of replacement or re-arrangement of existing cells to add a Trojan can be detected through rapid post-fabrication backside imaging.
[MICRO 2023] R. Agrawal, L. Castro, C. Juvekar, A. Chandrakasan, V. Vaikuntanathan, and A. Joshi, “MAD: Memory-Aware Design Techniques for Accelerating Fully Homomorphic Encryption” to appear in IEEE/ACM International Symposium on Microarchitecture (MICRO) 2023.
[MICRO 2023] K. Shivdikar, Y. Bao, R. Agrawal, M. Shen, G. Jonatan, E. Mora, A. Ingare, N. Livesay, J. Abellan, J. Kim, A. Joshi, and D. Kaeli, “GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption” to appear in IEEE/ACM International Symposium on Microarchitecture (MICRO) 2023.
[TVLSI 2023] Z. Azad, G. Yang, R. Agrawal, D. Petrisko, M. Taylor and A. Joshi, “RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption,” to appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI) 2023.
[JETC 2023] C. Demirkiran, F. Eris, G. Wang, J. Elmhurst, N. Moore, N. Harris, N. Basumallik, V. Reddi, A. Joshi and D. Bunandar, “An Electro-Photonic System for Accelerating Deep Neural Networks,” to appear in ACM Journal on Emerging Technologies in Computing Systems (JETC) 2023.
[ISLPED 2023] G. Yang, C. Demirkiran, Z. Kizilates, C. Ocampo, A. Coskun, and A. Joshi, “Processing-in-Memory using Optically-Addressed Phase Change Memory,” to appear in Proc. International Symposium on Low Power Electronics and Design (ISLPED) 2023. PDF
[SNAP-MLSys 2023] C. Demirkiran, R. Agrawal, V. Reddi, D. Bunandar and A. Joshi, “Leveraging Residue Number System for Designing High-Precision Analog Deep Neural Network Accelerators,” in Workshop on Systems for Next-Gen AI Paradigms (SNAP), co-located with Conference on Machine Learning and Systems (MLSys) 2023. PDF
[SLCA 2023] R. Agrawal and A. Joshi, “Architecting Computing Systems for Fully Homomorphic Encryption,” Synthesis Lectures on Computer Architecture (SLCA) 2023. Link
[IEEE MICRO 2023] N. Livesay, G. Jonatan, E. Mora, K. Shivdikar, R. Agrawal, A Joshi, J. L. Abell ́an, J. Kim, D. Kaeli, “Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs,” in Proc. IEEE Micro 2023. PDF
[HOST 2023] S. Canakci, C. Rajapaksha, A. Nataraja, L. Delshadtehrani, M. Taylor, M. Egele and A. Joshi, “ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance,” in Proc. IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2023. (BEST PAPER AWARD) PDF
[DATE 2023] C. Rajapaksha, L. Delshadtehrani, M. Egele and A. Joshi, “SIGFuzz: A Framework for Discovering Microarchitectural Timing Side Channels,” in Proc. Design, Automation and Test in Europe (DATE) 2023. PDF
[HPCA 2023] R. Agrawal, L. DeCastro, G. Yang, C. Juvekar, R. Yazicigil, A. Chandrakasan, V. Vaikuntanathan and A. Joshi, “FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption,” in Proc. IEEE International Symposium on High-Performance Computer Architecture (HPCA) 2023. PDF
[TACO 2022] F. Eris, M. Louis, K. Eris, J. Abellan and A. Joshi, “Puppeteer: A Random Forest-based Manager for Hardware Prefetchers across the Memory Hierarchy,” in ACM Transactions on Architecture and Code Optimization (TACO) 2022. PDF
[TACO 2022] A. Narayan, Y. Thonnart, P. Vivet, A. Coskun and A. Joshi, “Architecting Optically-Controlled Phase Change Memory,” in ACM Transactions on Architecture and Code Optimization (TACO) 2022. PDF
[PACT 2022] Y. Bao, Y. Sun, Z. Feric, M. Shen, M. Weston, J. L. Abellán, T. Baruah, J. Kim, A. Joshi and D. Kaeli, “NaviSim: A Highly Accurate GPU Simulator for AMD RDNA GPUs,” in Proc. International Conference on Parallel Architectures and Compilation Techniques (PACT) 2022. PDF
[SEED 2022] K. Shivdikar, G. Jonatan, E. Mora, N. Livesay, R. Agrawal, A. Joshi, J. L. Abellán, J. Kim and D. Kaeli, “Accelerating Polynomial Multiplication for Homomorphic Encryption on GPUs,” in Proc. IEEE International Symposium on Secure and Private Execution Environment Design (SEED) 2022. PDF
[HOTCHIPS 2022] N. Harris, D. Bunandar, A. Joshi, A. Basumallik and R. Turner, “Passage: A Wafer-Scale Programmable Photonic Communication Substrate,” in Proc. IEEE Hot Chips Symposium (HCS) 2022. PDF
[ISLPED 2022] Z. Azad, G. Yang, R. Agrawal, D. Petrisko, M. Taylor and A. Joshi, “RACE: RISC-V SoC for En/decryption ACceleration on the Edge for Homomorphic Computation,” in Proc. International Symposium on Low Power Electronics and Design (ISLPED) 2022. PDF
[ISMRM 2022] M. Louis, H. Liao, R. Singh, J. Lee, A. Joshi and A. Lin. “Using Machine Learning to Identify Metabolite Spectral Patterns that Reflect Outcome after Cardiac Arrest,” in International Society for Magnetic Resonance in Medicine (ISMRM) Annual Meeting & Exhibition 2022.
[ISMRM 2022] M. Louis, H. Liao, A. Joshi and A. Lin. “The Effect of Differences in MRS Parameters on Data Harmonization of Normative Data,” in International Society for Magnetic Resonance in Medicine (ISMRM) Annual Meeting & Exhibition 2022.
[ASIACCS 2022] S. Canakci, N. Matyunin, K. Graffi, A. Joshi and M. Egele, “TargetFuzz: Using DARTs to Guide Directed Greybox Fuzzers,” in Proc. ACM ASIA Conference on Computer and Communications Security (ASIACCS) 2022. PDF
[DATE 2022] P. Das, A. Joshi and H. Kapoor, “Hydra: A Near Hybrid Memory Accelerator for CNN Inference,” in Proc. Design, Automation and Test in Europe (DATE) 2022. PDF
[SPRINGER 2022] Y. Ma, B. Joardar, P. Pande and A. Joshi, “Interconnect and Integration Technology” to appear in Emerging Computing: From Devices to Systems – Looking Beyond Moore and Von Neumann, Springer Nature 2022.